1. Field of the Invention
The present invention relates to a silicon carbide semiconductor device, and more particularly to a JBS (Junction Barrier controlled Schottky diode) or an MPS (Merged P-i-N/Schottky diode) which uses silicon carbide.
2. Description of the Background Art
The dielectric breakdown electric field of silicon carbide is about ten times as large as that of silicon and the band gap of silicon carbide is about three times as wide as that of silicon. Therefore, a power device using silicon carbide has a characteristic feature that allows a high temperature operation with low resistance as compared with a currently-used power device using silicon.
Particularly, an SBD (Schottky Barrier Diode) and a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) which use silicon carbide can reduce a loss in an operation as compared at the same breakdown voltage with a pn diode and an IGBT (Insulated Gate Bipolar Transistor) which use silicon. The Schottky barrier diode (SBD), especially, has a simple device structure, and development thereof for practical use has been actively made.
The Schottky barrier diode (SBD) has problems of an increase in the leak current in application of reverse bias and an increase in a loss in energization in a case where it is intended to achieve high breakdown voltage. As a countermeasure against these problems, proposed are a JBS, an MPS, and the like structures. The JBS is a structure in which an N-type epitaxial layer is formed on an N+, -type silicon carbide substrate and a Schottky electrode is formed in a front surface of the N−, -type epitaxial layer and an ohmic electrode is formed on a back surface of the N+, -type silicon carbide substrate. A P-type end region for relieving an electric field is provided at an end portion of the Schottky electrode and a P-type region is provided below the Schottky electrode.
In any structure, a P-type region is formed below the Schottky electrode, at the end portion of the Schottky electrode, and at a peripheral portion thereof.
In techniques disclosed, for example, in Japanese Patent Application Laid Open Gazette Nos. 2008-282973, and 2008-300506,, P-type regions of different depths and P-type regions of different sizes are formed below the Schottky electrode.
Further, in techniques disclosed in Japanese Patent Application Laid Open Gazette Nos. 2008-270413, and 2011-521471,, P-i-N regions are arranged in a unit of chip. In a technique disclosed in Japanese Patent Application Laid Open Gazette No. 2008-042198,, P-type regions of two kinds of concentrations are arranged in a unit of chip.
For achieving the above structures, however, in order to form the P-type regions of different conditions, ion implantation has to be performed the number of times that satisfies the different conditions. Therefore, there arises a problem of an increase in the number of ion implantation processes.
Further, since the P-type regions are locally formed, surge current is concentrated and this arises a problem that high breakdown voltage cannot be achieved.